#ifndef _PARTHUS_SYS_HAL_FEATURES_H
#define _PARTHUS_SYS_HAL_FEATURES_H

/***********************************************************************
 *
 * MODULE NAME:    sys_hal_features.h
 * PROJECT CODE:   BlueStream
 * DESCRIPTION:    Platform specific feature configuration
 * MAINTAINER:     John Sheehy
 * DATE:           March 08 2001
 *
 * SOURCE CONTROL: $Id: sys_hal_features.h,v 1.32 2009/12/23 11:39:43 tianwq Exp $
 *
 * LICENCE:
 *    This source code is copyright (c) 2001-2004 Ceva Inc.
 *    All rights reserved.
 *
 * REVISION HISTORY:
 *    08 March 2001 - Initially added by JS
 *
 ***********************************************************************/

/*
 * Any platform specific configurable features (e.g. UART baud rate)
 * should go in this module.
 */

/*
 * Transport plane options
 */

#if (BUILD_TYPE==UNIT_TEST_BUILD)
#define TRA_HCIT_GENERIC_SUPPORTED 1
#else
#define TRA_HCIT_GENERIC_SUPPORTED 0
#endif

/* uart is alway support for debug */
#define TRA_HCIT_UART_SUPPORTED 1

#if (COMBINED_HOST==1) /* combined chips */

#define TRA_HCIT_COMBINED_SUPPORTED 0
#define TRA_HCIT_BCSP_SUPPORTED     0
#define TRA_HCIT_SPI_SUPPORTED      0
#define TRA_HCIT_I2C_SUPPORTED      0
#define TRA_HCIT_USB_SUPPORTED      0

#elif(RDA_PRODUCT==RDA_MOBILE_CHIP) /* chip for mobile device */

#define TRA_HCIT_COMBINED_SUPPORTED 0
#define TRA_HCIT_BCSP_SUPPORTED     1
#define TRA_HCIT_SPI_SUPPORTED      0
#define TRA_HCIT_I2C_SUPPORTED      0
#define TRA_HCIT_USB_SUPPORTED      0

#elif(RDA_PRODUCT==RDA_STANDARD_CHIP) /* all transport support */
#define TRA_HCIT_COMBINED_SUPPORTED 0
#define TRA_HCIT_BCSP_SUPPORTED     1
#define TRA_HCIT_SPI_SUPPORTED      0
#define TRA_HCIT_I2C_SUPPORTED      0
#define TRA_HCIT_USB_SUPPORTED      1

#else /* dongle product */

#define TRA_HCIT_COMBINED_SUPPORTED 0
#define TRA_HCIT_SPI_SUPPORTED      0
#define TRA_HCIT_I2C_SUPPORTED      0
#define TRA_HCIT_BCSP_SUPPORTED     0

#if (RDA_PRODUCT == RDA_USB_DONGLE)
#define TRA_HCIT_USB_SUPPORTED      1
#else
#define TRA_HCIT_USB_SUPPORTED      0
#endif

#endif

#define TRA_HCIT_PCMCIA_SUPPORTED   0

#define TRA_HCIT_UART_ONLY_SUPPORTED            0

#if (BUILD_EMULATION ==1) && (BUILD_MEMORY_MAP == 0)
#define TRA_HCIT_UART_DEFAULT_BAUD_RATE        115200
#else
#define TRA_HCIT_UART_DEFAULT_BAUD_RATE        115200
#endif
#define TRA_HCIT_UART_HIGH_BAUD_RATE           921600

#define TRA_HCIT_UART_SET_BAUD_RATE_IMMEDIATE   1

#define TD_RF                                   1
#define DEBUG_UART_ENABLE	0
#define FPGA_MODE_ENABLE	0//0 for ascii mode; add by xzc
#define SYS_SYN_VIA_AHB2DSP_ENABLE 0

/* 20081125 zys: add flag for using 26MHz OSC. of mobile */
#if(RDA_PRODUCT==RDA_STANDARD_CHIP)||(RDA_PRODUCT==RDA_MOBILE_CHIP) /* chip for mobile device */
#define RDA_USE_MOBILE_26MHz_OSC                1
#define RDA_CO_WIFI_SUPPORT                     1
#else
#define RDA_USE_MOBILE_26MHz_OSC                0
#define RDA_CO_WIFI_SUPPORT                     0
#endif

#if (COMBINED_HOST==1) /* combined chips */
#define RDA_WATCHDOG_SUPPORT                    1
#define RDA_PMU_SUPPORT                         1
#else
#define RDA_WATCHDOG_SUPPORT                    0
#define RDA_PMU_SUPPORT                         0
#endif
/*
 * XR7 Specific UART section
 *
 * On the XR7, only UART1 has the 16 byte FIFOs, (the
 * others have only 4)
 * while only UART2 has the modem control feature
 */

#if (COMBINED_HOST==1)
#define XR7_HCIT_UART 1
#else
#define XR7_HCIT_UART 2
#endif

#if XR7_HCIT_UART == 1
    #define HCIT_CHIMERA_16550_RECV_FIFO_TRIGGER    1
    #define HCIT_CHIMERA_16550_TX_FIFO_LENGTH       1
    #define HCIT_CHIMERA_16550_TX_FIFO_LENGTH_SPP       511
    #define HCIT_CHIMERA_USE_CTSRTS                 0
#elif XR7_HCIT_UART == 2
    #define HCIT_CHIMERA_16550_RECV_FIFO_TRIGGER    1
    #define HCIT_CHIMERA_16550_TX_FIFO_LENGTH       480
    #define HCIT_CHIMERA_USE_CTSRTS                 0
#else
    #error Please define XR7_HCIT_UART to be either 1 or 2
#endif

/*
 * There seems to be a problem with the interrupt unit on
 * the XR7 UARTs, whereby under heavy stress conditions,
 * the UART will miss a transmit interrupt, thus causing
 * the HCI transport to be permanently "stuck" in the busy
 * state. To alleviate this, the following option enables
 * the polled mode. This is guaranteed to work, but is far
 * more cpu intensive (the CPU must spin on the status of
 * a register rather than sleep and wait for an interrupt)
 */

#define TRA_HCIT_UART_POLLED_TX_SUPPORTED           1


/*
 * Memory limit values for POST (Power on Self Test)
 * These are for the AEB-1, Chimera needs different values
 */

#ifdef BUILD_FOR_ROM
    #define SYSpost_LSRAM_START_ADDR 0x00000000
    #define SYSpost_LSRAM_END_ADDR   0x00000800

    #define SYSpost_SRAM_START_ADDR  0x00000810
    #define SYSpost_SRAM_END_ADDR    0x00040800
#else
    #define SYSpost_LSRAM_START_ADDR 0x00000800
    #define SYSpost_LSRAM_END_ADDR   0x00001000

    #define SYSpost_SRAM_START_ADDR  0x00000800
    #define SYSpost_SRAM_END_ADDR    0x00001000
#endif

/*
 *
 */
#define SYS_LF_OSCILLATOR_PRESENT   1

#endif /* _PARTHUS_SYS_HAL_FEATURES_H */
